The invention relates to manufacture of semiconductor devices, and more particularly, to a method for forming a low stress composite inter metal dielectric layer (IMD).
Inter metal dielectric layers (IMD) have been used in the semiconductor industry to passivate underlying metal interconnect structures, as well as to provide isolation of these same metal interconnect structures. Low k dielectric layers, such as hydrogen silsesquioxane (HSQ), and fluorinated silicon oxide glass (FSG) have provided the desired passivation, and isolation characteristics, as well as offering decreased capacitances, when compared to higher k dielectric layers, such as silicon oxide. The superior passivation characteristics of silicon oxide layers, such as minimum leakage and high dielectric breakdown strengths, however, make it an attractive candidate for IMD purposes, when compared to lower k dielectric layer counterparts.
One problem encountered with IMD layers, comprised of chemically vapor deposited silicon oxide layers, is the inherent stress of these layers, and the damage placed thereby on underlying elements of the semiconductor device. For example, an IMD layer can be a composite IMD layer, comprising an underlying layer, an IMD-1 component, such as a plasma enhanced silicon oxide layer formed using silane as a precursor, an IMD-2 component, featuring a sub-atmospheric chemically vapor deposited (SACVD) silicon oxide layer, or a capping plasma enhanced silicon oxide layer (IMD-3) component formed using tetraethylorthosilicate, (TEOS) as precursor. The IMD-2 component, in this case SACVD silicon oxide, which is required to provide the desired gap filling, inherently comprises a high tensile stress, which induces unwanted bowing up or down of the underlying semiconductor substrate.
This type of bowing can result in cracking of underlying insulator layers, as well as disruptions or opens in underlying metal interconnect patterns. The capping dielectric layer, or the IMD-3 component, formed by plasma enhanced chemical vapor deposition, using TEOS as a source, inherently comprises a compressive stress, which supplies a convex or bowing down effect on the underlying semiconductor and elements thereof. The degree of compressive stress, provided by the IMD-3, PETEOS silicon oxide layer, formed using conventional deposition methods, however, may be insufficient to overcome the high tensile stress of the IMD-2, SACVD silicon oxide component, therefore the deleterious bowing up or down effects may still occur.
IMD cracking due to stress can be eliminated by reducing IMD-2 thickness, but a thinner IMD-2 layer would result in bad gap-filling. Additionally, the above described cracks can also be eliminated by increasing RF power or O2/TEOS ratio, but high RF power reduces the life span of chamber parts, and film deposited by high RF power has poor wafer to wafer uniformity and unstable film stress.
Another disadvantage of the conventional TEOS deposition method is shown in FIG. 1. Voids 10 are easily formed near the surface of the IMD film 20 between two metal patterns due to slow TEOS deposition rate. Thus, voids 10 are likely to be exposed during subsequent chemical mechanical polish (CMP) process, generating leakage or reliability problems.
U.S. Pat. No. 6,121,164 discloses a method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about −5×108 dynes/cm2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer. U.S. Pat. No. 6,426,285 discloses using TEOS as a source, and using a set of power, and frequency conditions, resulting in a high compressive stress for the capping silicon oxide layer.